SPI1_INV0=0, SPI1_INV2=0, AFEOUTCLKSEL=0, TMRFREEZE=0, SPI1_INV1=0, SPI1_INV3=0, SPI0_INV1=0, LPUARTSRC=00, ADCTRGSEL=00, PLLFLLSEL=00, SPI0_INV3=0, SPI0_INV2=0, NMIDIS=0, XBARCLKOUT=000, CLKOUT=000, SPI0_INV0=0
System Control Register
| NMIDIS | NMI Disable 0 (0): NMI enabled 1 (1): NMI disabled |
| PLLVLPEN | PLL VLP Enable |
| ADCTRGSEL | SAR ADC Trigger Clock Select 0 (00): Bus ClockDuring Low Power Modes such as stop, the Bus clock is not available for conversion and should not be selected in case a conversion needs to be performed while in stop. 1 (01): ADC asynchronous Clock 2 (10): ERCLK32K 3 (11): OSCCLK |
| CLKOUT | Clock out Select 0 (000): Disabled 1 (001): Gated Core Clk 2 (010): Bus Clk 3 (011): LPO clock from PMC 4 (100): IRC clock from MCG 5 (101): Muxed 32Khz source (please refer to SOPT1[19:18] for possible options) 6 (110): MHz Oscillator external reference clock 7 (111): PLL clock output from MCG |
| SPI0_INV0 | This bit inverts the SPI0 signal output. 0 (0): not inverted 1 (1): inverts SS |
| SPI0_INV1 | This bit inverts the SPI0 signal output. 0 (0): not inverted 1 (1): inverts SCK |
| SPI0_INV2 | This bit inverts the SPI0 signal output. 0 (0): not inverted 1 (1): inverts MOSI |
| SPI0_INV3 | This bit inverts the SPI0 signal output. 0 (0): not inverted 1 (1): inverts MISO |
| SPI1_INV0 | This bit inverts the SPI1 signal output. 0 (0): not inverted 1 (1): inverts SS |
| SPI1_INV1 | This bit inverts the SPI1 signal output. 0 (0): not inverted 1 (1): inverts SCK |
| SPI1_INV2 | This bit inverts the SPI1 signal output. 0 (0): not inverted 1 (1): inverts MOSI |
| SPI1_INV3 | This bit inverts the SPI1 signal output. 0 (0): not inverted 1 (1): inverts MISO |
| PLLFLLSEL | PLL/FLL selection 0 (00): MCGFLLCLK 1 (01): MCGPLLCLK 2 (10): BUSCLK 3 (11): OSC32KCLK (RTC Oscillator output) |
| XBARCLKOUT | XBAR clock out selection 0 (000): Disabled 1 (001): Gated Core Clk 2 (010): Bus Clk 3 (011): LPO clock from PMC 4 (100): IRC clock from MCG 5 (101): MUXed 32 kHz source (please refer to SOPT1[19:18] for possible options) 6 (110): MHz Oscillator external reference clock 7 (111): PLL clock output from MCG |
| AFEOUTCLKSEL | AFE clock output select 0 (0): AFE output clock is divided by AFE clock prescaler. 1 (1): AFE output clock is NOT divided by AFE clock prescaler. |
| LPUARTSRC | LPUART clock Source configuration 0 (00): Clock disabled 1 (01): MCGPLLCLK/MCGFLLCLK 2 (10): OSCERCLK 3 (11): MCGIRCLK |
| TMRFREEZE | QTMR counters Freeze control 0 (0): QTMR counters operate normally. 1 (1): QTMR counters and OFLAGs are reset. Clearing this bit will resume QTMR operation. |